Cupertino, CA

• Silicon Engineering Group (SEG)
• Directed the design and development of an embedded application which dynamically predicts latencies of critical HW IP blocks in real-time, detecting bandwidth starvation, surges, and idling. Enabled for critical workflows, providing detailed HW insights and potential optimizations on data access, caching patterns and bandwidth bottlenecks.
• Ultimately resulted in a 15% caching improvement for key end-user use-cases. Analyzed and eased various bandwidth bottlenecks by 20% through software pre-fetching algorithms and proposed HW design changes.
• Designed and implemented a live on-device dashboard, broadcasting performance metrics on multiple HW IPs simultaneously. Allowed for a comprehensive view and replay capabilities for SoC debugs.
• Spearheaded the HW bring-up of multiple IP Blocks across a range of SoCs as the Organization’s Subject Matter Expert. Collaborated and iterated with hardware architecture and CoreOS for production use-cases.
• Led the team in architecting and accelerating a custom large-scale data engineering platform. Improved performance and visualizations speeds by 500%, and memory usage up to 4000%. Introduced distributed caching schemes and parallel data processing for additional performance gains. Platform speeds and memory profiling surpassed Apache Spark for many of the department's use-cases.
• Technologies: C/C++, RTOS, ARM, Python, Rust, Distributed System Design.

West Lafayette, IN

Cupertino, CA

• On the Silicon Engineering Group (SEG)
• Developed embedded solutions for analyzing and optimizing performance on Apple SOCs.
• Worked on an in-house RTOS; Designed features to interface and interact with hardware architecture, primarily to identify/resolve memory bandwidth bottlenecks.

Melbourne, FL

• Developed embedded solutions on an ARM Controller for upcoming product releases, focusing on optimizing features for better product performance.
• Worked throughly to integrate custom FPGA hardware with embdeded software.
• Produced several design reviews and conducted code reviews.
• In-depth details are confidential as per US Title-18.

Seattle, WA

• Worked on AMP, internal metadata search engine for applications, reports, and data. Using predictive analysis and machine learning models to classify users under personas to improve “relevancy” for search results.
• Developed an NLP model to identify abstract “topics” from searches to improve user experience and search efficiency.

Chicago, IL

• Worked with Order Entry division of the GLOBEX platform. Developed a wrapper and implemented fault tolerance across Market Segment Gateway (MSGW) instances with FT daemons.
• Implemented a dynamic state sync across all connected distributed systems: client systems, order entry systems, and matching engine. Improved team’s SDLC by over 30% with FT implementation.
• Developed programs to reduce regression report runtime on AWS EC2.
• Experienced in SDLC Agile environment working with distributed system architecture.
• 2019 CME CodeUp - Won 3rd Place developing an efficient trading algorithm on derivative markets.